1. Technical Field
The present invention generally pertains to the field of maintenance and diagnostic control of computer devices. In particular, it pertains to a method and apparatus for single step clocking of the computer device where signal paths exceed one clock cycle in length.
2. Background Art
It is well known in the art that single-stepping or N-stepping of computer system clocks is an essential tool in the debug and maintenance of computer systems. Single-stepping allows the computer state to be observed both immediately prior and immediately after the execution of a system clock cycle, while N-stepping allows similar observation over any number of system clock cycles. In the past, there has been little difficulty in providing N-step capability to computer systems. All that is required is the ability to controllably enable or disable the system clock at the request of the engineer performing debug or maintenance operations. However, in high performance computers having short clock cycles, merely controlling the system clock may not be sufficient to provide N-step capability to the computer. This is particularly true of high-speed supercomputers of the type produced by the assignee of the present invention.
Supercomputers are typically designed as synchronous machines, with internal data generated by a source latch during one clock cycle being used at a destination latch during a subsequent clock cycle. Although the internal data can propagate from the source latch to the destination latch very quickly, there is a certain amount of time between when the data leaves the source latch and when it arrives at the destination latch. If the system clock cycle is shorter than this propagation time, then data generated by the source latch on multiple successive clock cycles would be present in the signal path simultaneously, prior to any of the data reaching the destination latch.
This causes little problem in normal operation, with the destination latch being designed to expect data two or more clock cycles after its generation by the source latch. However, such an arrangement causes serious problems with the ability of the computer to function during stop and restart of the system clock. For example, if the system clock is stopped after receipt by the destination latch of the first data from the source latch, then the second data from the source latch which is already in the signal path will be lost. The problem occurs when attempting to restart the system clock, in that the data intended for the destination latch during the upcoming clock cycle has been lost and is no longer present on the signal path.
The traditional solution to this problem was to reduce the physical size of the computer as much as possible, eliminating all signal paths in excess of one clock cycle in length. While this alleviates the N-step problem, it places a limit on the complexity with which a computer can be designed. This is because given any particular computer technology, there are physical limitations to the amount of circuitry that can be placed in a given volume of space. Requiring only single clock length signal paths limits the available volume, which in turn limits the amount of circuitry and thus the circuit complexity.
Furthermore, there is tremendous competitive advantage in the supercomputer market for improved performance, and one way to improve the performance of supercomputers is to reduce the clock cycle time. This further limits the available space for circuitry and circuit complexity, which may actually limit the performance of the supercomputer.
As supercomputers become more complex and are designed with shorter clock cycles, there is an increasing desire to not be limited to signal paths shorter than a single clock cycle in length. Accordingly, there is a need for supercomputers to be able to stop, restart and N-step system clocks over signal paths in excess of one clock cycle in propagation length.